PIC16C62B/72A
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 73
RETFIE
Return from Interrupt
Syntax:
[
label ]
RETFIE
Operands:
None
Operation:
TOS
→ PC,
1
→ GIE
Status Affected:
None
RETLW
Return with Literal in W
Syntax:
[
label ]
RETLW k
Operands:
0
≤ k ≤ 255
Operation:
k
→ (W);
TOS
→ PC
Status Affected:
None
Description:
The W register is loaded with the eight
bit literal ’k’. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
RETURN
Return from Subroutine
Syntax:
[
label ]
RETURN
Operands:
None
Operation:
TOS
→ PC
Status Affected:
None
Description:
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two cycle instruction.
RLF
Rotate Left f through Carry
Syntax:
[
label ]
RLF
f,d
Operands:
0
≤ f ≤ 127
d
∈ [0,1]
Operation:
See description below
Status Affected:
C
Description:
The contents of register ’f’ are rotated
one bit to the left through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
stored back in register ’f’.
RRF
Rotate Right f through Carry
Syntax:
[
label ]
RRF f,d
Operands:
0
≤ f ≤ 127
d
∈ [0,1]
Operation:
See description below
Status Affected:
C
Description:
The contents of register ’f’ are rotated
one bit to the right through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
placed back in register ’f’.
SLEEP
Syntax:
[
label ]
SLEEP
Operands:
None
Operation:
00h
→ WDT,
0
→ WDT prescaler,
1
→ TO,
0
→ PD
Status Affected:
TO, PD
Description:
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its pres-
caler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 10.13 for more details.
Register f
C
Register f
C
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